The invention relates to a method and an apparatus for switching frame-oriented serial data, in particular PCM data in communications systems.
In GSM mobile radio systems, in switching speech and data in the various system components, the problem arises that eight kbit/s channels (one bit per PCM frame and multiples thereof) have to be switched. For instance, a half-rate channel has a bandwidth of eight kbit/s in GSM mobile radio systems at the interface Asub between the base station controller BSC and the transcoding unit TRAU and at the interface Abis between the base station BTS and the transcoding unit TRAU. A full-rate channel, on the other hand, has a bandwidth of 16 kbit/s. Switching should if at all possible be done without blocking, freely selectably and with a fixed guaranteed delay of one PCM frame (125 xcexcsec). Similar problems arise in other communications systems as well.
In order to effect such switching, for instance in processing 16 kbit/s channels, it has been necessary to date to map a PCM frame with a data rate of 2 Mbit/s onto a PCM frame of eight Mbit/s. The information is transmitted four times to the switching apparatus and there switched to a 64-kbit/s base, and after switching the information is again mapped to 2 Mbit/s. This requires major expenditure for circuitry and attendant high costs. Such a task can be accomplished only to a limited extent using standard components. An implementation with standard components requires a large amount of space, which rises disproportionately with the number of channels. Present circuits do not assure that all the bits of an input frame will be transmitted together in the next output frame. Switching the last bit of input frame to the first bit of the next output frame makes very high demands. Yet this switching option is desirable, if channels of arbitrary bandwidth (nxc3x978 kbit/s) are switched (for instance, the H11 channel in ISDN with 1536 kbit/s), without tearing apart the information in a channel.
It is accordingly an object of the invention to provide a method and a device for transmitting frame-oriented serial data, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which switches PCM data so that channels of largely arbitrary bandwidth (nxc3x978 kbit/s) and a high data throughput can be switched at a predetermined clock frequency.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of switching frame-oriented serial data, which comprises:
reading at least a first portion of serial data into an input RAM via an interface;
reading the data from the input RAM into a switching unit;
controlling a read/write operation of the input RAM with a central controller;
generating switching information with the central controller according to a switching algorithm, whereby the switching information is related to the data bit by bit and includes addresses of output lines of the interface;
controlling a switching unit with a control signal and
controlling the switching information with the central
controller;
switching the data with the switching unit bit by bit to the output lines of the interface in accordance with the switching information; and
outputting the data via the interface.
By means of the bit by bit switching, data from channels of largely arbitrary bandwidth can be switched without passing through the switching apparatus multiple times. The apparatus is advantageously embodied as an applications-specific circuit.
In accordance with an added feature of the invention, the generating step comprises generating in the switching information, in addition to the addresses of the output lines, a bit-referred chronological order of a data output.
In accordance with an additional feature of the invention, the switching algorithm is stored in a switching RAM.
In accordance with another feature of the invention, a readout of the switching information, a readout of the data from the input RAM, and switching of the data in the switching unit is effected in parallel operation.
In accordance with a further feature of the invent ion, a bypass data path is defined in the interface and a second portion of the data is carried directly from the input of the interface to the output lines under control of the central controller via the bypass data path in the interface.
In accordance with again an added feature of the invention, single bits or a plurality of cohesive bits of the second portion of the data are switched through from an end region of an input frame to a front region at a beginning of an output frame to be output.
In accordance with again an additional feature of the invention, the interface is a PCM interface, and the method comprises transmitting the frame-oriented serial data in PCM frames.
In accordance with again another feature of the invention, the data is read out from the interface into a background region of the input RAM, while the data from a foreground region of the input RAM are read out into the switching unit, and the foreground and background regions are transposed after a frame has been processed.
In accordance with again a further feature of the invention, the data switched by the switching unit are read into a background region of an output register, while the data from the foreground region are output to the output lines.
In accordance with yet an added feature of the invention, at least two bits are switched in parallel in the switching unit and they are stored.
In accordance with yet an additional feature of the invention:
a starting address is generated by an address mapping algorithm via a reading table from a number of a respective output line;
an intermediate data set is generated from an OFFSET address via a control data set, so that different data rates can be taken into account;
the intermediate data set and the starting address are linked together, and starting bits of the data set generated in the linking step are transposed, such that the switching information for the bits of one output line are distributed to non-cohesive cells of the switching RAM, so that in quasi-sequential processing of the switching RAM, the bits are read out of the input RAM in an order in which they are chronologically required for each output line.
In accordance with yet another feature of the invention, the linking of the intermediate data set and the starting address is additive linking.
In accordance with yet an additional feature of the invention, the quasi-sequential processing comprises reading out equidistant cells of the switching RAM in succession.
In accordance with a further feature of the invention, a data rate to be processed is selected in a frame of the switching algorithm, and an equal data rate is configured on all the output lines or different data rates on individual output lines or groups of output lines.
With the above and other objects in view there is also provided, in accordance with the invention, an apparatus for switching frame-oriented serial data, which comprises:
an input RAM and a plurality of output lines;
a PCM interface connected to the output lines and to the input RAM, the PCM interface reading a first portion of serial data into the input RAM and outputting the data to the output lines;
a switching unit connected between the input RAM and the output lines, the switching unit receiving the data from the input RAM, switching the data bit by bit, and outputting the data to the output lines;
a central controller connected to the input RAM and to the switching unit, the central controller generating switching information with a switching algorithm wherein the switching information is referred to the data bit by bit and includes addresses of the output lines, and the central controller controlling a read/write operation of the input RAM and controlling the switching unit by means of a control signal and the switching information.
In accordance with yet again an added feature of the invention, a switching RAM is provided which stores an address mapping algorithm, and wherein a readout of the switching information from the switching RAM, a readout of the data from the input RAM, and a switching of the data in the switching unit are effected in parallel mode.
In accordance with yet again another feature of the invention, the PCM interface has an input register and a bypass data path including a bypass register into which bypass bits are read, under control of the central controller, from the input register of the PCM interface.
In accordance with a concomitant feature of the invention, a multiplexer is connected downstream of the bypass register, the multiplexer outputting the data of the bypass data path and the data of the first portion of the data to the output lines under control of the central controller.
By means of a bypass data path, it is readily possible to switch the last bit of an incoming PCM frame to the first bit of the next PCM data frame. Each arbitrary bit of an input frame can thus be switched with a fixed delay of one PCM frame (125 xcexcsec). By means of the parallel but still bit-by-bit switching of a plurality of bits, the data rate can be increased. The parallel mode of data processing, in an advantageous feature of the invention, assures that a high data throughput of 2, 4 or 8 Mbit/s will be attained.
According to the invention, a non-blocking switching for up to 4096xc3x978 kbit/s channels is attained (32 MBit/s maximum throughput at 16,384 MHz), because switching is done bit by bit, so that a genuine bit switch is used. Moreover any arbitrary multiple of 8 kbit/s (nxc3x978 kbit/s, where n=1, . . . , 1024) in any arbitrary combination as a channel is possible.
One advantageous embodiment of the method of the apparatus shows how the switching information is distributed in the switching RAM. Already on being written into the switching RAM, the data are distributed in such a way that in the ensuing readout of the various identical physical addresses of four RAMs, the required switching information is output in the correct order.
In another advantageous feature of the invention, a method is disclosed for which there is a demand, especially in the mobile radio field (especially for half-rate applications) and other fields that do not use multiples of 64 kbit/s. Each PCM input line and output line can be configured entirely freely to two or four or eight Mbit/s, so that a line can be physically turned off or need not be present, or operation can be effected at three different data rates. This degree of freedom is a substantial advantage of the exemplary embodiment of the apparatus known as BISON (for bit switch for optimized network architectures) for switching the data, compared with conventional circuits. The BISON component is a programmable PCM switching component whichxe2x80x94as shown in the exemplary embodimentxe2x80x94has all the functions for realizing the desired information flow in a way that is as simple as possible.
In further advantageous features of the invention, the throughout and/or the number of input and output lines can be increased. In other words, a plurality of BISON components can be combined in cascadable fashion into a switching matrix of arbitrary size; the outputs on a bit basis can be put in the tristate condition. With the BISON component, switching matrices of arbitrary size and for channels of various bandwidths can therefore be constructed substantially less expensively than before. In addition, the switching matrices can be constructed in a substantially more space-saving way than before.
In accordance with another feature of the invention, two or more of the above-described apparatus are connected to one another for switching frame-oriented serial data.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in method and apparatus for switching frame-oriented serial data, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.